With increasing demands for multi-functional miniaturized electronic devices, it is expected to integrate more and more devices on a wafer. However, current devices have already been so miniaturized to approach physical limits, and thus it is more and more difficult to further reduce an average area per device. Further, any area penalty may result in increased cost.
One of solutions to follow the trend of miniaturization is 3D devices, such as, FinFETs (Fin Field Effect Transistors). The FinFETs have reduced footprints on a wafer surface by extending in a height direction. However, as compared with planar devices such as MOSFETs, more areas are occupied by isolation between FinFETs because each isolation requires two dummy gates.